HSCC---Hardware/Software Cooperative Caching for Hybrid DRAM/NVM Memory Architectures

       HSCC is implemented with zsim and NVMain simulators. Zsim is a fast x86-64 multi-core simulator. It exploits Intel Pin toolkit to collect traces of memory accesses for processes, and replays the traces in the zsim simulator. NVMain is a cycle-accurate memory simulator, it models components of DRAM and NVMs, and memory hierarchy in detail. The integrated "zsim + NVMain" simulators can be forked from "https://github.com/AXLEproject/axle-zsim-nvmain".

Based on the "zsim + NVMain" hybrid simulator, HSCC has added the following functions:

The architecture and modules of HSCC are shown in the following figure: Image of Yaktocat

Origianl License & Copyright of zsim

zsim is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, version 2.

zsim was originally written by Daniel Sanchez at Stanford University, and per Stanford University policy, the copyright of this original code remains with Stanford (specifically, the Board of Trustees of Leland Stanford Junior University). Since then, zsim has been substantially modified and enhanced at MIT by Daniel Sanchez, Nathan Beckmann, and Harshad Kasture. zsim also incorporates contributions on main memory performance models from Krishna Malladi, Makoto Takami, and Kenta Yasufuku.

zsim was also modified and enhanced while Daniel Sanchez was an intern at Google. Google graciously agreed to share these modifications under a GPLv2 license. This code is (C) 2011 Google Inc. Files containing code developed at Google have a different license header with the correct copyright attribution.

Additionally, if you use this software in your research, we request that you reference the zsim paper ("ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems", Sanchez and Kozyrakis, ISCA-40, June 2013) as the source of the simulator in any publications that use this software, and that you send us a citation of your work.

License & Copyright of HSCC (HUST SCTS & CGCL Lab)

HSCC is implemented by Yujie Chen, Dong Liu and Haikun Liu at Cluster and Grid Computing Lab & Services Computing Technology and System Lab in Huazhong University of Science and Technology(HUST SCTS & CGCL Lab), the copyright of this HSCC remains with CGCL & SCTS Lab of Huazhong University of Science and Technology.

Citing HSCC

If you use HSCC, please cite our reearch paper published at ICS 2017, included as doc/HSCC.pdf.

Haikun Liu, Yujie Chen, Xiaofei Liao, Hai Jin, Bingsheng He, Long Zhen and Rentong Guo, Hardware/Software Cooperative Caching for Hybrid DRAM/NVM Memory Architectures, in: Proceedings of the 31st International Conference on Supercomputing (ICS'17), Chicago, IL, USA, June 14-16, 2017

@inproceedings{Liu:2017:HCC:3079079.3079089,
 author = {Liu, Haikun and Chen, Yujie and Liao, Xiaofei and Jin, Hai and He, Bingsheng and Zheng, Long and Guo, Rentong},
 title = {Hardware/Software Cooperative Caching for Hybrid DRAM/NVM Memory Architectures},
 booktitle = {Proceedings of the International Conference on Supercomputing},
 series = {ICS 2017},
 year = {2017},
 isbn = {978-1-4503-5020-4},
 location = {Chicago, Illinois},
 pages = {26:1--26:10},
 articleno = {26},
 numpages = {10},
 url = {http://doi.acm.org/10.1145/3079079.3079089},
 doi = {10.1145/3079079.3079089},
 acmid = {3079089},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {caching, hybird memory, non-volatile memory (NVM)},
}

Setup,Compiling and Configuration

1.External Dependencies
       Before install hybrid simulator zsim-nvmain, it's essential that you have already install dependencies listing below.

2.Compiling

3.zsim Configuration Keys (example zsim configuration files is in zsim-nvmain/config directory)

(4) sys.mem.zone: memory management configuration zone_dma/zone_dma32/zone_normal/zone_highmem: set OS zone size(MB)
(5) sys.enable_shared_memory: true, enable shared memory simulation ( default is true )

TLB, Page Table and Memory Management Simulation Modules

       As described above, original zsim doesn't support OS simulation, and HSCC has added TLB, page table and memory management simulation into zsim. The major modifications are shown in the following figure. The left side presents the major code of original zsim corresponding to system simulation, the right side describes HSCC modifications to zsim for TLB, page table and memory management simulation support. Image of Yaktocat

Architecture of HSCC

        HSCC has extended both page table and TLB to maintain both virtual-to-NVM and NVM-to-DRAM address mappings. HSCC also develops an utility-based DRAM caching policy that only fetching hot pages into DRAM cache when the DRAM is under high pressure to reduce DRAM cache pollution. HSCC also supports DRAM cache bypassing mechanism. The following figure shows the architecture of HSCC.Image of Yaktocat

Implementations of RBLA and MultiQueue Policies

Support or Contact

HSCC is developed at SCTS&CGCL Lab (http://grid.hust.edu.cn/) by Yujie Chen, Haikun Liu and Xiaofei Liao. For any questions, please contact Yujie Chen([email protected]), Haikun Liu ([email protected]) and Xiaofei Liao ([email protected]).